Automatic Generation of Error Control Codes

| This paper proposes a methodology, implemented in a tool, to automatically generate the main classes of Error Control Codes (ECCs) widely applied in computer memory systems to increase reliability and data integrity. New code construction techniques extending the features of previous Single Error Correcting (SEC)-Double Error Detecting (DED)-Single Byte Error Detecting (SBD) codes have been integrated in the tool. The proposed techniques construct systematic odd-weight-column SEC-DED-SBD codes with Odd-bit-per-byte Error Correcting (OBC) capabilities to enhance reliability in high speed memory systems organized as multiple-bit-per-chip or card. The proposed tool chooses the best suited error control code for the characteristics of the application and the design constraints and returns the VHDL description of the encoding/decoding circuits. The tool has been successfully applied for the design of a 64 data bit ECC contained in an ASIC designed for a multiprocessor system.